Hexus

Reconfigurable 'Jenga' CPU cache memory system proposed

Researchers at MIT’s Computer Science and Artificial Intelligence Lab have designed a system where programs can have access to ad hoc optimally allocated cache memory. In a simulation test system with ...
EDN

Last-level cache has become a critical SoC design element

As AI workloads extend across nearly every technology sector, systems must move more data, use memory more efficiently, and respond more predictably than traditional design methodologies allow. These ...
Electronic Design

Adding Cache to IPs and SoCs

Cache memory significantly reduces time and power consumption for memory access in systems-on-chip. Technologies like AMBA protocols facilitate cache coherence and efficient data management across CPU ...
Electronic Design

CXL Switch SoC Unlocks More Memory for AI

Check out our coverage of the 2023 Flash Memory Summit. This article is also part of the TechXchange: CXL for Memory and More. PCI Express (PCIe) is the de facto standard peripheral interface. Running ...
EDN

Memory Hierarchy Design – Part 5. Crosscutting issues and the memory design of the ARM Cortex-A8

This section describes three topics discussed in other chapters that are fundamental to memory hierarchies. Protection and Instruction Set Architecture Protection is a joint effort of architecture and ...