EDN

Complex SoC Testing with a Core-Based DFT Strategy

With scaling technology and increasing design sizes, power consumption during test and test data volume have grown dramatically &#8212 making it almost impossible to test an entire design once it ...
Semiconductor Engineering

Shift Left In DFT Design

The semiconductor industry continues to face numerous challenges as designs approach reticle limits, process nodes evolve and engineering resources become increasingly stretched. It is essential to ...
Electronic Design

DFT Strategies for SOC Designs

Many IC designers finally have embraced design for testability (DFT) in the form of scan insertion for digital circuit designs because of the significant time-to-production advantages these techniques ...
Semiconductor Engineering

Hierarchical DFT On A Flat Layout Design

The use of hierarchical DFT methods is growing as design size and complexity stresses memory requirements and design schedules. Hierarchical DFT divides the design into smaller pieces, creates test ...
EDN

ITC: DeFacTo unveils DFT product that eliminates need for gate-level scan

DeFacTo Technologies announced at the International Test Conference a new DFT product that analyzes a register-transfer level (RTL) integrated-circuit design, creates appropriate RTL scan-test ...