Electronic Design

Rule Checker Takes RTL Analysis Into The Physical Realm

At one time, the relationship between logic designers and physical implementation specialists was simpler. Front-end designers had long been accustomed to providing their ASIC vendors with a ...
Semiconductor Engineering

Earlier SoC Design Exploration And Verification Gets Better Designs To Tapeout Faster

Between the complexity of advanced node design verification and the competition to be first to the market, system-on-chip (SoC) designers no longer have the luxury of waiting until each sub-block of a ...
Electronic Design

Formal Verification Moves Into Design Phase

Traditionally, formal verification is used after the fact for bug hunting or design-rule checking. It has yet to be applied up front, where it would affect design decisions at the RTL coding stage.
EDN

LG Adopts In-Design Physical Verification with IC Compiler and IC Validator after Multiple Successful Tapeouts

Synopsys' In-Design physical verification with IC Validator and IC Compiler place-and-route solution accelerates LG Electronics' manufacturing closure by two weeks Multiple successful tapeouts using ...
Semiconductor Engineering

Let’s Do The (IC Design) Time Warp Again

For the most part, we’ve all been doing integrated circuit (IC) and system-on-chip (SoC) layout the same way for decades. Designers put together the design, be it intellectual property (IP), block, or ...