Design-Reuse

Open-source Framework and Practical Considerations for Translating RTL VHDL to SystemC

SystemC has gained wide acceptance in the design of new digital IPs. However, there are numerous IPs already designed in VHDL. With the advances in SystemC ecosystem, like IEEE standardization, TLM-2 ...
Design-Reuse

Optimization Methodologies for Cycle-Accurate SystemC Models Converted from RTL VHDL

IP design-houses are hard-pressed by their customers to provide SystemC models of their portfolio IPs, despite already existing VHDL views. VHDL IPs can be translated to SystemC, ensuring correctness, ...
EDN

Control Synthesis Output with Combinatorial Logic in Procedural Code

While it is tempting to write RTL and let the synthesis tool take over, this isn’t the best way to get the results we want. In this article, we’ll learn how to create complex combinatorial code in ...